1. Field of the Invention
The present invention relates to a semiconductor device, a semiconductor package and a memory repair method, and specifically relates to a semiconductor device provided with a repair circuit for repairing a defective bit in a memory inside the device, a semiconductor package and a memory repair method.
2. Description of the Related Art
Conventionally, there are circuits configured to repair defects in a memory. For example, a semiconductor memory device including a fuse circuit, a row redundancy section and an I/O redundancy section in an embedded memory in order to repair a defect in the embedded memory, (for example, see Japanese Patent Application Laid-Open Publication No. 2006-302464).
In recent years, for example, a technique called SiP (System in Package) in which a memory with a large capacity is stacked on a semiconductor chip and enclosed in a single package has been used. Consequently, chips that have conventionally been separated into two packages can be enclosed in a single package, enabling reduction of the mounting area, and thus, enabling, for example, downsizing of mobile phones.
However, where a memory is stacked on a semiconductor chip, it is necessary to properly connect the semiconductor chip and the memory using a technique called micro bumping or bonding, but memory defects occur at a small percentage due to thermal stress during this connection, and thus, it is necessary to perform a test again.
Where a memory is stacked on a semiconductor chip, but the memory connected as a result of being stacked includes no circuit configured to repair a memory defect, a test for repairing the memory defect cannot be performed, and thus, the occurred memory defect cannot be repaired.
Meanwhile, where a memory is stacked on a semiconductor chip, and the memory connected as a result of being stacked includes a circuit configured to repair a memory defect, a test for repairing the memory defect is performed for the memory, obtaining repair information for the memory defect. Subsequently, based on the repair information, blow processing of an eFuse circuit is performed, for example. Furthermore, depending on the repair circuit included in the memory, it is necessary to perform a test for examining whether or not the blow processing of the eFuse circuit has correctly been performed.
As described above, even a memory connected as a result of being stacked including a circuit configured to repair a memory defect has a problem that a large amount of time may be required for this series of processing, increasing the test cost.